Informatics Publishing Limited

R. Angayarkanni ¹, R. Arunprasath ²

Affiliations
1 Department of VLSI, Anna University, Regional Office, Madurai, IN
2 Anna University, Regional Office, Madurai, IN

Abstract

An on-chip network used to support traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. This paper also proposes a fault-tolerant solution for a buffer less network-on-chip, including an on-line fault-diagnosis mechanism to detect faults by using fault tolerant deflection routing algorithm. By removing the excessive overhead of queuing buffers, a compact implementation is achieved and stacking multiple networks to support concurrent permutations in runtime is feasible.

Keywords

Multiprocessors System on Chip, Multistage Interconnection Network, Permutation Networks.

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B. Lakshmi ¹, R. Arunprasath ²

Affiliations
1 Department of VLSI, Anna University, Regional Office, Madurai, IN
2 Anna University Regional Office, Madurai, IN

Abstract

To prevent soft errors from causing data corruption, memories are typically protected with error correction codes. An advanced error correction codes are used when an additional protection is needed. The majority logic decoder/detector codes are used for memory application because of correcting large number of soft errors, less decoding time, area consumption. The EG-LDPC codes are suitable for error correction using majority logic decoder/detector. Because the EG-LDPC codes are small, powerful and easily implemented in terms of decoding latency and complexity and this design achieving very high data rate while minimizing complexity. The proposed improved majority logic decoder/detector to perform silent data error detection in simple way using additional error detection technique and also reducing the area of the majority gate using sorting network. Hence the decoding process uses less number of cycles, reduces the area and also reducing the power consumption.

Keywords

EG-LDPC Code, Error Correction Codes, Majoritylogic Decoding, Memory.

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